UJA1061 Datasheet, PDF (24/81 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
Entering Selective Sleep out of Off-line is possible when
the CAN wake-up filter has been passed and the CPNC bit
has been set previously to logic 1. In contrast with entering
On-line out of Off-line, the wake-up flag is not set, so not
resulting in any activity of V1 and the microcontroller.
Selective Sleep mode will also be entered out of On-line in
case bit CPNC becomes logic 1. If the wake-up flag was
set, it will be cleared.
Another possibility for entering Selective Sleep mode is
resetting the CM bit in Active mode with bit CPNC set
logic 1.
If the CAN-bus has been dominant or recessive
continuously for the off-line time (t_offline), Off-line will be
entered.
The second possibility to leave Selective Sleep and enter
Active mode is by software control, possible by setting the
CAN mode bit logic 1.
A third possibility to leave Selective Sleep is by entering
On-line, possible only after detection of a dedicated Global
Wake-up CAN message. This comprises two messages
using any CAN identifier but a dedicated data pattern, first
the CAN wake-up message pattern and second the
Confirmation message pattern:
• CAN wake-up message: 0xC6 EE EE EE EE EE EE EF
• Confirmation message: 0xC6 EE EE EE EE EE EE 37.
There may be any other CAN message frame between the
two message patterns.
The maximum message separation time period has to be
less than t_timeout. If Selective Sleep was entered out of
Off-line due to bus activity, the message separation timer
will start directly without waiting for the first wake-up
message data pattern. The Confirmation message data
pattern, received before the overflow of the timer, is then
sufficient to go to On-line. Whenever Selective Sleep is
left, the Selective Sleep control bit is cleared again
automatically.
Within Sleep mode, any wake-up event is automatically
forwarded to the system reset due to power-up on V1.
(LOW) or INTN (LOW) if programmed accordingly.
In On-line, pin RXDC is held LOW until the CAN mode bit
is set successfully, or the CAN physical layer enters
Selective Sleep by setting the CPNC bit logic 1.
Once the bus becomes recessive or dominant for a certain
time (t_offline) the transceiver enters Off-line. The Off-line
timer is programmable in two steps with the CAN Off-line
Timer Control (COTC) bit. Entering Off-line will set the
timer to the longest period independently of the COTC bit
and will be reset with every CAN wake-up event
6.7.2 TERMINATION CONTROL
In Active mode, On-line and Selective Sleep, RTH and
RTL are strongly terminated to ground and to V2
respectively. The Normal Bus-Failure Management (BFM)
(known from the TJA1054/TJA1054A) is active. During
short-circuits at CANL and/or CANH, the corresponding
RTL or RTH pin becomes floating. When V2 is OFF or
unstable, both pins become floating and the Normal BFM
is left. A floating SYSINH results immediately in a
switch-over towards floating RTH and RTL and skipping
the Normal BFM because V2 level soon can fall.
6.7.3 BUS, RXD AND TXD FAILURE DETECTION
The UJA1061 can distinguish between bus, RXD and TXD
failures as indicated in Table 1.
All failures will be signalled separately to a 4-bit register.
Any change (detection and recovery) will give an interrupt
to the microcontroller, if enabled (limited to only one
interrupt per watchdog period). Polling of the SPI register
is always possible.
6.7.3.1 GND shift detection
Two different GND shift levels can be detected,
programmable by the microcontroller. Any detected or
recovered GND shift event results in an interrupt of the
microcontroller, if enabled (limited to only one interrupt per
watchdog period).
6.7.1.5 Off-line
Within Off-line the CAN physical layer becomes
automatically terminated towards an internal power
supply, supplied out of BAT42. V2 is disabled in order to
save supply current. Any CAN wake-up event
automatically restarts V2, entering On-line or Selective
Sleep. Wake-up is signalled via RXDC (LOW) and RSTN
2004 Mar 22
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