UJA1061 Datasheet, PDF (11/81 Pages) NXP Semiconductors – Low speed CAN/LIN system basis chip

Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
If Standby mode is entered out of Normal mode with
selected watchdog-off option, the watchdog uses the
maximum time-out defined for Standby mode until the
supply current drops below the current detection
threshold. Now the watchdog is off. If the current increases
again the watchdog will become active immediately using
the maximum watchdog time-out period again.
Generally, the microcontroller can be activated out of
Standby mode via a system reset or via an interrupt
without reset. This allows different start-up behaviours out
of Standby mode to be implemented, depending on
application needs:
• If the watchdog is still running during Standby mode, the
watchdog can be used for cyclic wake-up behaviour of
the system. A dedicated Watchdog Time-out interrupt
Enable (WTE) bit allows a decision whether the
microcontroller should receive an interrupt or a
hardware reset upon overflow. The interrupt option will
be cleared in hardware automatically with each
watchdog overflow to make sure that a failing main
routine is detected while the interrupt service still
operates. Therefore the application software must set
the interrupt behaviour again before the next standby
cycle is entered.
• Any wake-up via the CAN or the LIN bus as well as a
local wake-up event will force a system reset event or an
interrupt to the microcontroller. So it is possible to leave
Standby mode without any system reset if desired.
Upon an interrupt event the application software has to
read the interrupt register within 256 ms. If this is not
executed, the fail-safe system reset is forced and Start-up
mode is entered. If the application has read out the
interrupt register in time, it can decide to switch into
Normal mode via SPI access or to stay in Standby mode.
The following operations are possible within Standby
mode:
• Cyclic wake-up by the watchdog via an interrupt signal
to the microcontroller (the microcontroller is triggered
periodically and checked for the correct response)
• Cyclic wake-up by the watchdog via a reset signal (a
reset is performed periodically; the UJA1061 provides
information about the reset source in order to allow
different start sequences after reset)
• Wake-up by bus activity on CAN or LIN via an interrupt
signal to the microcontroller
• Wake-up by bus activity on CAN or LIN via a reset signal
• Wake-up by increasing microcontroller supply current
without a reset signal (where a stable supply is needed
for the microcontroller RAM contents to remain valid and
wake-up comes from an external application not
connected to the UJA1061)
• Wake-up by increasing microcontroller supply current
with reset signal
• Wake-up due to an edge at pin WAKE forcing an
interrupt to the microcontroller
• Wake-up due to an edge at pin WAKE forcing a reset
signal.
6.2.6 SLEEP MODE
Within Sleep mode the microcontroller power supply (V1)
and the INH controlled external supplies are switched off
entirely thus resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out
mode or is completely OFF.
Entering Sleep mode results in an immediate LOW level
on pin RSTN, thus stopping any operation of the
microcontroller. In parallel, the INH output is floating and
pin V1 is disabled. Only SYSINH could remain active to
support the V2 voltage supply; this depends on CAN
programming. It is also possible for V3 to be ON, OFF or
in Cyclic mode in order to supply external wake-up
switches.
If the watchdog is not disabled in software, the watchdog
keeps running and forces a system reset upon overflow of
the programmed period time. The UJA1061 enters
Start-up mode and pin V1 becomes active again. This
behaviour could be used for a cyclic wake-up out of Sleep
mode.
Entering Sleep mode can be done only from Normal mode
or from Standby mode with a mode change via the SPI.
Depending on the application, the following operations are
selectable within Sleep mode:
• Cyclic wake-up by the watchdog (only in Time-out
mode); a reset is performed periodically, the UJA1061
provides information about the reset source in order to
allow different start sequences after reset
• Wake-up by bus activity on CAN or LIN
• Wake-up due to a falling edge at pin WAKE
• An overload on V3, only if V3 is in a cyclic or in
continuously-on mode.
2004 Mar 22
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