TDA8024 Datasheet, PDF (6/29 Pages) NXP Semiconductors – IC card interface

Philips Semiconductors
IC card interface
Product specification
TDA8024
7 PINNING
SYMBOL
PIN TYPE
DESCRIPTION
CLKDIV1
CLKDIV2
5V/3V
PGND
S2
V_DDP
S1
V_UP
PRES
PRES
I/O
AUX2
AUX1
CGND
CLK
RST
V_CC
PORADJ
CMDVCC
RSTIN
V_DD
GND
OFF
XTAL1
XTAL2
I/OUC
AUX1UC
AUX2UC
1
I CLK frequency selection input 1
2
I CLK frequency selection input 2
3
I
card supply voltage selection input; V_CC = 5 V (HIGH) or V_CC = 3 V (LOW)
4
S DC/DC converter power supply ground
5
I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
6
S DC/DC converter power supply voltage
7
I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
8
I/O DC/DC converter output decoupling capacitor connection; C = 100 nF with
ESR < 100 mW must be connected between V_UP and PGND
9
I card presence contact input (active LOW); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
10
I card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
11
I/O data line to/from card reader contact C7; integrated 11 kΩ pull-up resistor to V_CC
12
I/O data line to/from card reader contact C8; integrated 11 kΩ pull-up resistor to V_CC
13
I/O data line to/from card reader contact C4; integrated 11 kΩ pull-up resistor to V_CC
14
S card signal ground
15
I/O card clock to/from card reader contact C3
16
O card reset output from card reader contact C2
17
S card supply voltage to card reader contact C1; decoupled to CGND via 2 × 100 nF
or 100 + 220 nF capacitors with ESR < 100 mΩ; note 1
18
I Power-on reset threshold adjustment input for changing the reset threshold with
an external resistor bridge; doubles the width of the POR pulse when used; this
pin is not connected for the TDA8024AT
19
I input from the host to start activation sequence (active LOW)
20
I card reset input from the host
21
S supply voltage
22
S ground
23
O NMOS interrupt output to the host (active LOW); 20 kΩ integrated pull-up resistor
to V_DD
24
I crystal connection or input for external clock
25
O crystal connection (leave open-circuit if external clock source is used)
26
I/O host data I/O line; integrated 11 kΩ pull-up resistor to V_DD
27
I/O auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to V_DD
28
I/O auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to V_DD
Note
1. The noise margin on V_CC will be higher with the 220 nF capacitor.
2004 July 12
6