SA1620 Datasheet, PDF (6/26 Pages) NXP Semiconductors – Low voltage GSM front-end transceiver

Philips Semiconductors
Low voltage GSM front-end transceiver
Product specification
SA1620
Table 2. DC Regulators
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN
LIMITS
TYP
UNITS
MAX
V_BATT
Common positive input voltage at both regulators
VREG1+0.3
VREG1,
VREG2
Output voltages of regulators 1 and 2
V_BATT = 3.3V
2.85
3
V
3.15
V
I_INT1
I_INT2
I_INT01, I_INT02
I_VREG1MAX5
I_VREG2MAX5
BW⁶
Internal current of REG1 in power-on mode
Internal current of REG2 in power-on mode
Internal current in power-down mode
Max output current at VREG1
Max output current at VREG2
V_BATT = 3.3V, I_REG1 = 0.1mA
V_BATT = 3.3V, I_REG1 = 100mA
V_BATT = 7.5V, I_REG1 = 100mA
≤100kHz
4 + I_VREG1/10
mA
2.5 + I_VREG2/10
mA
<15
µA
100
mA
30
mA
0.03
60
kHz
80
≤–61
F_REG7
f
10MHz
100MHz
≤–32
dB
≤–37
400MHz
≤–48
NOTES:
1. Power-on pin of Regulator 1 and 2: PON
2. Input currents at PON: <1µA. There are no pull-up or pull-down resistors.
3. Feedthrough attenuation from the logic input PON to the outputs VREG1 and VREG2: ≥40dB.
4. Recommended load capacitors: C529 = C530 = 1µF to ground with series resistance ≤0.1Ω. See Figure 4. Additional optional capacitor
≤1000µF with series resistance ≤5Ω.
5. At T_j ≥ 150°C a thermal switch reduces the output current.
6. Typical open loop bandwidths of regulator 1 at V_REG1 = 3V and C529 = 1µF.
7. Feedthrough attenuation (at the indicated frequency f) from the input V_BATT to the outputs V_REG1 and V_REG2 at V_BATT = 3.3V,
(CON1=CON2=L)
1997 May 22
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