SA1620 Datasheet, PDF (12/26 Pages) NXP Semiconductors – Low voltage GSM front-end transceiver

Philips Semiconductors
Low voltage GSM front-end transceiver
Product specification
SA1620
Overview of Dual GSM/PCN Architecture
The SA1620 RF front-end and SA1638 IF transceivers form a dual
conversion architecture which uses a common IF and standard I/Q
baseband interface for both transmit and receive paths. This
approach avoids the screening difficulties of direct modulation in the
transmit direction and the mass production and practical
performance issues related to direct conversion in the receive
direction. The time division multiplex nature of the GSM system
permits integration of the transmit and receive functions together on
the one RF and one IF chips. This simplifies the distribution of local
oscillator signals, maximizes circuitry commonality, and reduces
power consumption.
The SA1620 and SA1638 allow considerable flexibility to optimize
the transceiver design for particular price/size/performance
requirements, through choice of appropriate RF and IF filters. The
receive IF may be chosen freely in the range 70–500MHz, while the
transmit IF is fixed to 400 MHz. The comparison frequency of the
SA1638 PLL is high in order to provide fast switching time.
With suitable choice of the IF, an identical SA1638 IF receiver
design can be used for both 900MHz GSM and 1800MHz PCN
(DCS1800) equipment.
General Benefits/Advantages
• 2.7V operation. Compatible with 3V digital technology and
portable applications. (Higher voltage operation also possible, if
desired.)
• Excellent dynamic range. The availability of two LNAs allows
flexibility in receiver dynamic design for portable and mobile GSM
spec. applications with appropriate filters. If for a particular
application a GaAs or discrete front-end is desired, one of the
LNAs can be left unpowered. The placing of the AGC gains
switches at the front means that for most of the time some
attenuation will be inserted, further increasing typical dynamic
performance beyond that specified by GSM.
• High power transmit output driver, delivering +8.5dBm output.
This is sufficient to drive a filter and power amplifier input, without
a driver amplifier. To avoid unnecessary current consumption the
output power can be reduced, if not required, by appropriate
choice of an external resistor.
• DC offsets generated in the receive channel are independent of
the AGC setting, and correctable by software to prevent erosion of
signal handling dynamic range by DC offsets. Independence of
DC from AGC setting is achieved by putting the gain switches in
the RF front-end.
• Minimal high-quality filter requirements. As a result of the
integration in the SA1638 of high quality channel selectivity filters,
only sufficient filtering is needed in the receive path to provide
blocking protection for the second mixers. This reduces receiver
cost and size.
• Operation at a high IF allows RF image reject filters to be relaxed.
For example, at a 400MHz IF, the natural gain roll-off in the LNAs
and mixer suppresses the image signal in the 1800MHz band by
typically 28dB below the desired 900MHz band signal.
Receive Path
Multiple LNAs allow the flexibility to exploit the best choice of
currently available filters (on performance, size, or cost grounds).
This approach is preferable to a single high-gain stage as the stray
cross-coupling effects between pins remain manageable. In a single
stage amplifier this would limit the amount of rejection of out-of-band
signals that could be achieved, and would also limit the amount of
AGC attenuation that could be practically implemented.
The LNAs are powered up only when PONBUF, PDTx and PONRx
are high, to allow a high degree of battery economy. If greater
sensitivity is required for an application, an external preamplifier
circuit can be used instead of LNA1, and LNA1 left unconnected.
A special mode is provided with just the IF output related circuitry
active in order to allow calibration of the DC offset at the SA1638
baseband receive outputs. This offset contains a contribution due to
coupling effects between the second local oscillator and the IF
circuitry, and therefore the receiver is set up in the receive state (but
with incoming signals excluded) to allow accurate offset calibration.
Gain Control
Gain control is implemented in the SA1620 RF front-end. This
avoids the disruption of the DC offset at the baseband IQ outputs
that is typically caused by changes in the AGC. The SA1620 and
SA1638 are designed so that the GSM dynamic range requirements
can be met with the AGC remaining on the maximum gain setting.
These gain steps scale the dynamic range of the received signal
(e.g., 90dB for GSM) into the dynamic range of the baseband
processing device.
The absolute gain tolerances may be measured together with the
attenuation tolerances of external filters during production of the
receiver equipment. After software calibration switching from one
dynamic range to another will cause only minor errors.
Tx Path
TXIF and TXIFX are differential IF inputs for phase modulated
signals (e.g., GMSK). There is an IF level control loop which
provides a constant amplitude to an image reject up mixer. Thus,
this mixer operates linearly in the IF path, independent of IF level
tolerances.
The single sideband up mixer is sufficient in quadrature to achieve
the typical performance indicated in Table 6 over an IF range of 250
to 500MHz. The mixer is operating in switching mode by well
matched 0° and 90° LO signals, optimized for 1.1 to 1.5GHz.
The Tx output stage operates in switching mode. Thus, parasitic
AM at the IF is not transferred. The outputs TXO and TXOX may be
used symmetrically or single-ended. Some spurious emissions will
be very low when a symmetrical output signal is used.
P_OUT = R_e ^ƪ6.25V @ (Z_{Pin 40} ) Z_{Pin 41}) @ (I_R546)^2ƫ
according to Figure 4 and
I_R546
+
V_R546
R₅₄₆
according
to
DC
Electrical
Characteristics. P_OUT is adjustable with R546 and is accurate to
within ±1dB over the full voltage range 2.7 to 5.5V, and ±0.5dB from
a given supply voltage. The absolute limit of the negative peak
voltage swing at pins TxO and TxOX is V_SAT = V_CCTx1,2 – 1V. The
absolute limit of the positive peak voltage is +6V.
1997 May 22
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