PSMN7R8-120ES_15 Datasheet, PDF(6/13 Page) NXP Semiconductors – N-channel 120 V 7.9 mΩ standard level MOSFET in I2PAK

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PSMN7R8-120ES_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel 120 V 7.9 mΩ standard level MOSFET in I2PAK

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NXP Semiconductors

PSMN7R8-120ES

N-channel 120 V 7.9 mÎ© standard level MOSFET in I2PAK

Symbol

Parameter

Conditions

internal gate

f = 1 MHz

resistance (AC)

Dynamic characteristics

QG(tot)

QGS

total gate charge

gate-source charge

ID = 25 A; VDS = 60 V; VGS = 10 V;

Fig. 14; Fig. 15

QGS(th)

pre-threshold gate-

source charge

QGS(th-pl)

post-threshold gate-

source charge

QGD

gate-drain charge

VGS(pl)

gate-source plateau

voltage

ID = 25 A; VDS = 60 V; Fig. 14; Fig. 15

Ciss

input capacitance

VDS = 60 V; VGS = 0 V; f = 1 MHz;

Coss

output capacitance

Tj = 25 Â°C; Fig. 16

Crss

reverse transfer

capacitance

td(on)

turn-on delay time

rise time

VDS = 60 V; RL = 2.4 Î©; VGS = 10 V;

RG(ext) = 5 Î©; Tj = 25 Â°C

td(off)

turn-off delay time

fall time

Source-drain diode

VSD

source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 Â°C; Fig. 17

trr

reverse recovery time IS = 25 A; dIS/dt = -100 A/Âµs; VGS = 0 V;

recovered charge

VDS = 60 V

Min Typ Max Unit

167 -

36.9 -

24.2 -

12.7 -

50.5 -

4.5 -

9473 -

441 -

298 -

45.5 -

55.3 -

151.8 -

60.8 -

0.81 1.2 V

75.7 -

264 -

PSMN7R8-120ES

Product data sheet

All information provided in this document is subject to legal disclaimers.

18 February 2013

6 / 13

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