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| PSMN3R0-30YLD_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel 30 V, 3.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology | |||
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NXP Semiconductors
PSMN3R0-30YLD
N-channel 30 V, 3.0 mΩ logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
ÎVGS(th)/ÎT
gate-source threshold
voltage variation with
temperature
25 °C < Tj < 150 °C
IDSS
drain leakage current VDS = 24 V; VGS = 0 V; Tj = 25 °C
VDS = 24 V; VGS = 0 V; Tj = 125 °C
IGSS
gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
RDSon
drain-source on-state VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
resistance
Fig. 10
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 11; Fig. 10
RG
gate resistance
f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 15 V; VGS = 10 V;
Fig. 12; Fig. 13
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 12; Fig. 13
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13
Ciss
input capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 14
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf
fall time
Min Typ Max Unit
-
-4.3 -
mV/K
-
-
1
µA
-
0.82 -
µA
-
-
100 nA
-
-
100 nA
-
3.2 4
mΩ
-
-
6.6 mΩ
-
2.57 3.1 mΩ
-
-
5.1 mΩ
-
0.57 1.14 Ω
-
31
46.4 nC
-
14.5 21.9 nC
-
28.5 -
nC
-
4.9 -
nC
-
2.9 -
nC
-
2
-
nC
-
4.5 6.7 nC
-
2.75 -
V
-
1959 2939 pF
-
1029 1543 pF
-
140 210 pF
-
13.5 -
ns
-
21
-
ns
-
16.9 -
ns
-
12.4 -
ns
PSMN3R0-30YLD
Product data sheet
All information provided in this document is subject to legal disclaimers.
18 February 2014
© NXP N.V. 2014. All rights reserved
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