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| PSMN1R8-40YLC_15 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 40 V 1.8 mΩ logic level MOSFET in LFPAK using NextPower technology | |||
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NXP Semiconductors
PSMN1R8-40YLC
N-channel 40 V 1.8 m⦠logic level MOSFET in LFPAK using NextPower
technology
Symbol
Parameter
Conditions
RG
gate resistance
f = 1 MHz
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 20 V; VGS = 10 V;
Fig. 14; Fig. 15
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 15; Fig. 14
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
QGS(th)
gate-source charge
pre-threshold gate-
source charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 15; Fig. 14
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 20 V; Fig. 15; Fig. 14
Ciss
input capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 16
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf
fall time
Qoss
output charge
VGS = 0 V; VDS = 20 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
trr
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 20 V
ta
reverse recovery rise VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs;
time
VDS = 20 V; Fig. 18
tb
reverse recovery fall
time
Min Typ Max Unit
0.5 1
2
Ω
-
96
-
nC
-
45
-
nC
-
88
-
nC
-
15.5 -
nC
-
8.4 -
nC
-
7.1 -
nC
-
10.9 -
nC
-
2.7 -
V
-
6680 -
pF
-
825 -
pF
-
310 -
pF
-
32.2 -
ns
-
37
-
ns
-
62.5 -
ns
-
31.7 -
ns
-
30
-
nC
-
0.77 1.1 V
-
37
-
ns
-
43
-
nC
-
21
-
ns
-
16
-
ns
PSMN1R8-40YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
22 August 2012
© NXP B.V. 2012. All rights reserved
6 / 14
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