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PSMN018-80YS Datasheet, PDF (6/15 Pages) NXP Semiconductors – N-channel LFPAK 80 V 18 mΩ standard level MOSFET
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NXP Semiconductors
PSMN018-80YS
N-channel LFPAK 80 V 18 mΩ standard level MOSFET
6. Characteristics
Table 6. Characteristics
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown
voltage
gate-source threshold voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 10
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 125 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 5 A; Tj = 175 °C;
see Figure 12
VGS = 10 V; ID = 5 A; Tj = 100 °C;
see Figure 12
VGS = 10 V; ID = 5 A; Tj = 25 °C;
see Figure 12; see Figure 13
RG
internal gate resistance (AC)
Dynamic characteristics
f = 1 MHz
QG(tot)
QGS
QGS(th)
total gate charge
gate-source charge
pre-threshold gate-source
charge
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS(th-pl)
post-threshold gate-source
charge
QGD
VGS(pl)
gate-drain charge
gate-source plateau voltage
ID = 25 A; VDS = 40 V; see Figure
14; see Figure 15
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 40 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
VDS = 40 V; RL = 1.6 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
Min Typ Max Unit
73 -
-
V
80 -
-
V
1
-
-
V
-
-
4.6 V
2
3
4
V
-
-
2
µA
-
-
50 µA
-
-
100 nA
-
-
100 nA
-
-
43 mΩ
-
-
28 mΩ
-
15
18
mΩ
-
0.56 -
Ω
-
23
-
nC
-
26
-
nC
-
8
-
nC
-
4.7 -
nC
-
3.3 -
nC
-
6
-
nC
-
4.8 -
V
-
1640 -
pF
-
170 -
pF
-
95
-
pF
-
16
-
ns
-
8
-
ns
-
30
-
ns
-
7
-
ns
PSMN018-80YS
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 28 October 2010
© NXP B.V. 2010. All rights reserved.
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