TDA4885 Datasheet, PDF (47/56 Pages) NXP Semiconductors – 150 MHz video controller with I2C-bus

Philips Semiconductors
150 MHz video controller with I²C-bus
Product specification
TDA4885
13.1 Test application
For high frequency measurements a special test
application and printed-circuit board with only a few
external components is built. Figure 19 shows the test
application circuit and Figs 20 and 21 the layout of the
double sided printed board. Most components are of SMD
type. Short HF loops and minimum crosstalk between the
channels and between signal inputs and outputs are
achieved by properly shaped ground areas.
The HF input signal can be fed to the subclick connectors
V_I1, V_I2 and V_I3 by a 50 Ω line. The line is then terminated
by a 50 Ω resistor on the board. In channel 3 (pin 10) the
HF input signal can be measured (probe socket).
For operation without input clamping the DC bias can be
provided by VINDC if a short-circuit at J1, J2 and J3 is
made.
OSD input signals (subclick: OSD₁, OSD₂, OSD₃, FBL)
and blanking/clamping inputs (subclick: CLI, HFB) are
terminated with 50 Ω on the board.
The gain modulation input GM (subclick) can be
connected to the three inputs by the jumpers J8 and J4, J5
and J6. With jumper J7 pins 12, 13 and 14 can be
connected to ground (no gain reduction).
There is a separate 4-pin connector for the I²C-bus
controller, SDA and SCL have 10 kΩ pull up resistors to
5 V digital supply.
The beam current limiting pin is fed to the 10-pin main
connector without any special application and should be
connected to the 5 V supply if not used.
DC supply voltage V_P with a series resistor of 5.6 Ω can be
measured directly at pin 7 via a resistor of 1 kΩ
(V_P sense).
The supply voltage for the signal channels is fed to VPX
separately and connected to pins 19, 24 and 29 with
decoupling resistors of 5.6 Ω. The supply voltage V_P1
(pin 29) can be measured via 1 kΩ at pin V_P1 sense.
All supply voltages are filtered near to their pins with
150 pF and 100 nF SMD capacitors and low impedance
0.47 µF/63 V electrolytic capacitors.
The signal outputs are loaded with 10 kΩ and 3 pF to
ground and are connected to a probe socket. With a probe
capacitance of 2 pF the total capacitive load is 5 pF.
The feedback inputs are connected to the voltage outputs
with a 0 Ω resistor (short circuit; RFB1) and via 10 kΩ
(RFB2) connected to the pin VFBDC. The blanking level
can be adjusted with a variation of RFB1, RFB2 and
VFBDC but the resistive output load will be changed.
The blanking level is:
U_outbl
=


1
+
RR-----FF----BB-----12-- _
× 0.7
V – ^{RR-----FF----BB-----12--} × VFBDC
The reference outputs are connected to solder pins.
1997 Nov 25
47