TDA4885 Datasheet, PDF (18/56 Pages) NXP Semiconductors – 150 MHz video controller with I2C-bus

Philips Semiconductors
150 MHz video controller with I²C-bus
Product specification
TDA4885
3. Definition of output signals (see Fig.6):
Colour signal: all positive voltages referred to black level at signal outputs.
Nominal colour signal: colour signal with nominal input signal (0.7V_b-w), nominal contrast setting and maximum
gain setting.
Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the
superposing of the brightness information (∆V_bl) and the colour signal.
4. The total supply current I_P = I₇ + I₂₉ + I₂₄ + I₁₉ depends on the supply voltage with a factor of approximately 10 mA/V
and varies in the temperature range of −20 to +70 °C by approximately ±10% (V_{30, 25, 20} = 0.7 V).
5. The channel supply current depends on the signal output current, the channel supply voltage and the signal output
voltage. With I_px = I_{29, 24, 19} at V_{P1, 2, 3} = 8 V and V_{30, 25, 20} = 0.7 V:
I_{29, 24, 19} ≈ I_px + I_{30, 25, 20} + 3.1 ^m---V---A-- × ( V_{P1, 2, 3} – 8 V) – 2.5 ^m---V---A-- × ( V_{30, 25, 20} – 0.7 V)
6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and
if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V₅ = 1.2 to 3.5 V and vice
versa in less than 75 ns/V) no blanking will occur during input clamping.
For 75 ns/V < t_r/f5 ≤ 280 ns/V the generation of the internal vertical blanking pulse is uncertain, for t_r/f5 > 280 ns/V the
internal blanking pulse will be generated.
Pin 5 open-circuited will activate permanent input clamping and undefined blanking.
7. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the
signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding
clamping/blanking pulses via a resistor of some kΩ protects the pin from negative voltages.
8. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking
and output clamping.
9. The DC voltage during input clamping is temperature dependent with a factor of approximately 0.5 V/100 °C (3V_BE).
10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below
input reference black level (see Fig.3).
11. Contrast control acts on internal colour signals under I²C-bus control; subaddress 02H
(bit resolution 1.6% of contrast range).
12.
∆ G_track
=
20 × maximum of



log



A--A---₁^-1-₀^-
×
A--A---_2-2-0-



;
log



A--A---₁^-1-₀^-
×
A--A---_3-3-0-



;

log 

A--A---₂^-2-₀^-
×
A--A---_{3-3-0- }



dB
A_x: colour signal output amplitude in channel x at any contrast setting.
A_x0: colour signal output amplitude in channel x at nominal contrast and same gain setting.
13. When OSD fast blanking is active and V_{2, 3, 4} are HIGH (V₁ > 1.7 V, V_{2, 3, 4} > 1.7 V) the OSD colour signals will be
inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of
the inserted OSD signals can be controlled simultaneously by OSD contrast via I²C-bus.
14. Typical pulse at fast blanking input (pin 1) and response at signal outputs (pins 30, 25 and 20) with nominal input
signals at pins 6, 8 and 10.
15. Typical pulse at fast blanking input (pin 1) as well as OSD inputs (pins 2, 3 and 4) and response at signal outputs
(pins 30, 25 and 20) during OSD fast blanking for maximum OSD contrast, maximum gain adjustment and pins 12,
13 and 14 grounded. Small internal threshold and delay differences between fast blanking and signal insertion might
cause short signal distortion at begin and end of signal insertion (see Fig.10).
16. OSD contrast control acts on inserted OSD colour signals under I²C-bus control; subaddress 03H
(bit resolution 6.7% of OSD contrast range).
1997 Nov 25
18