TDA4885 Datasheet, PDF (19/56 Pages) NXP Semiconductors – 150 MHz video controller with I2C-bus

Philips Semiconductors
150 MHz video controller with I²C-bus
Product specification
TDA4885
17. This pin can be used for beam current limiting or subcontrast setting. Both the video and OSD contrast are reduced
simultaneously (see Figs 9 and 11). Because of the high-ohmic input impedance the pin should be tied to a voltage
of more than 5 V or applied with a capacitor of some nF if not used.
18. Brightness control adds an I²C-bus controlled DC offset to the internal colour signal; subaddress 01H
(bit resolution 1.6% of brightness range).
19. The voltage difference between video black level and reference black level is related to the colour signal with nominal
0.7 V (peak-to-peak value) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting.
The voltage difference is proportional to the gain setting (grey scale tracking). The given values of ∆V_bl are valid only
for video black levels higher than the signal output switch-off voltage V_{30, 25, 20(min)}.
20. Gain control acts on video signals and inserted OSD video signals under I²C-bus control; subaddress 04H
(channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range).
21. The usage of the gain modulation capability results in a reduction of the overall voltage gain of the TDA4885 but gives
enough room for positive and negative modulation. Only pins 12, 13 and 14 connected to ground makes it possible
to reach the specified maximum video signals at pins 30, 25 and 20 (see Fig.14). By short-circuiting pins 12, 13 and
14 it is possible to assure that the relations between the video signals remain constant for any modulation (common
gain modulation).
22. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative
signal at the signal output pins. The reference black level which should correspond to the ‘extended cut-off voltage’
at the cathodes is about ∆V_{30, 25, 20PED} higher (see Fig.5).
The use of pedestal blanking with AC-coupled cathodes (control bit FPOL = 1) allows a very simple black level
restoration with a DC diode clamp instead of a complicated pulse restoration circuit.
23. The signal-to-noise ratio is calculated by the formula (range 1 to 135 MHz):
N-S-- ^{= 20 × log p----e---a----k------t-o-------pR---e--M-a----kS----v--v-a--a--l-lu-u--e--e---o--o--f-f--t-t-h-h--e-e----n-n---o-o--m-i-s---ie-n----ao---l-u--s-t--pi-g--u--n-t--a--v-l--o-o--l--tu-a--t--gp---eu---t---v---o----l-t--a---g---e-- dB}
24. There might be short time smearing effects which have no thermal causes. The final amplitude will be reached some
10 ns after pulse step (amplitude differences of about 5%). For compensation methods see Section
“Recommendations for building the application board” in Chapter “Test and application information”.
25. Ideal input rise/fall time of 0 ns; t_{r2, out} = t_{r2, ideal} + t_{r2, in}
26. Crosstalk between any two output pins:
a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other
two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to
nominal (26H)
b) Output conditions: black level set to 1 V for each channel at signal outputs. Output signals are V_A and V_B
respectively
c) Transient crosstalk suppression: α_ct(tr) = 20 × log _V-V----^AB- dB
27. Internal feedback reference voltage acts under I²C-bus control for control bit FPOL = 0; subaddress 07H (channel 1),
08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). The internal feedback reference voltages
can be measured at feedback inputs (pins 31, 26 and 21) during output clamping (V₁₁ > 3.5 V) in closed feedback
loop. The feedback loop remains operative at output levels between typically 0.1 to 2.8 V. The reference voltages
are not influenced by the value of control bit PEDST. The levels of the internal feedback reference voltages depend
on the individual adjustments via I²C-bus (values from 00H to FFH) and the selected feedback polarity (control bit
FPOL = 0 or 1):
a) Control bit FPOL = 0: rising values of the data bytes (subaddresses 07H, 08H and 09H), e.g. 00H to FFH,
correspond to rising values of the resulting reference black levels at signal outputs (pins 30, 25 and 20)
b) Control bit FPOL = 1: the internal feedback reference voltage remains constant.
1997 Nov 25
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