SC16IS740 Datasheet, PDF (42/62 Pages) NXP Semiconductors – Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

NXP Semiconductors
SC16IS740/750/760
Single UART with I²C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 33 and Table 34 show the bits’ presentation at the subaddress byte for I²C-bus and
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I²C-bus interface, but it is used by the
SPI interface to indicate a read or a write operation.
S
SLAVE ADDRESS
W
A REGISTER ADDRESS⁽¹⁾ A
nDATA
A
P
White block: host to SC16IS740/750/760
Grey block: SC16IS740/750/760 to host
(1) See Table 33 for additional information.
Fig 22. Master writes to slave
002aab047
The register read cycle (see Figure 23) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal subaddress will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
S
SLAVE ADDRESS
W
A REGISTER ADDRESS⁽¹⁾ A
S
SLAVE ADDRESS
R
A
White block: host to SC16IS740/750/760
Grey block: SC16IS740/750/760 to host
(1) See Table 33 for additional information.
Fig 23. Master read from slave
nDATA
A
LAST DATA
NA
P
002aab048
Table 33.
Bit
7
6:3
2:1
0
Register address byte (I²C)
Name
Function
-
not used
A[3:0]
UART’s internal register select
CH1, CH0
channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
-
not used
SC16IS740_750_760_5
Product data sheet
Rev. 05 — 16 November 2006
© NXP B.V. 2006. All rights reserved.
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