SC16IS740 Datasheet, PDF(31/62 Page) NXP Semiconductors – Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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SC16IS740 Datasheet, PDF (31/62 Pages) NXP Semiconductors – Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.10 Enhanced Features Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows

the enhanced feature register bit settings.

Table 22. Enhanced Features Register bits description

Bit Symbol Description

EFR[7] CTS ï¬ow control enable

logic 0 = CTS ï¬ow control is disabled (normal default condition)

logic 1 = CTS ï¬ow control is enabled. Transmission will stop when a HIGH

signal is detected on the CTS pin.

EFR[6] RTS ï¬ow control enable.

logic 0 = RTS ï¬ow control is disabled (normal default condition)

logic 1 = RTS ï¬ow control is enabled. The RTS pin goes HIGH when the

receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when

the receiver FIFO resume transmission trigger level TCR[7:4] is reached.

EFR[5] Special character detect

logic 0 = Special character detect disabled (normal default condition)

logic 1 = Special character detect enabled. Received data is compared

with Xoff2 data. If a match occurs, the received data is transferred to FIFO

and IIR[4] is set to a logical 1 to indicate a special character has been

detected.

EFR[4] Enhanced functions enable bit

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],

MCR[7:5].

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]

so that they can be modiï¬ed.

3:0 EFR[3:0] Combinations of software ï¬ow control can be selected by programming these

bits. See Table 3 âSoftware ï¬ow control options (EFR[3:0])â.

8.11 Division registers (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLH stores the most signiï¬cant part of the divisor. DLL stores

the least signiï¬cant part of the divisor.

Note that DLL and DLH can only be written to before Sleep mode is enabled, that is,

before IER[4] is set.

SC16IS740_750_760_5

Product data sheet

Rev. 05 â 16 November 2006

31 of 62

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