SC16IS740 Datasheet, PDF (23/62 Pages) NXP Semiconductors – Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

NXP Semiconductors
SC16IS740/750/760
Single UART with I²C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.1 Receive Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX pin. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
8.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX pin. If
the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow
occurs.
8.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels. Table 11 shows FIFO Control Register bit settings.
Table 11. FIFO Control Register bits description
Bit Symbol
Description
7:6 FCR[7] (MSB), RX trigger. Sets the trigger level for the RX FIFO.
FCR[6] (LSB) _{00 = 8 characters}
01 = 16 characters
10 = 56 characters
11 = 60 characters
5:4 FCR[5] (MSB), TX trigger. Sets the trigger level for the TX FIFO.
FCR[4] (LSB) _{00 = 8 spaces}
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3 FCR[3]
reserved
2
FCR[2]^[1]
reset TX FIFO
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
level logic (the Transmit Shift Register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
1
FCR[1]^[1]
reset RX FIFO
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
level logic (the Receive Shift Register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
0 FCR[0]
FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO
SC16IS740_750_760_5
Product data sheet
Rev. 05 — 16 November 2006
© NXP B.V. 2006. All rights reserved.
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