TDA8051 Datasheet, PDF (4/24 Pages) NXP Semiconductors – QPSK receiver

Philips Semiconductors
QPSK receiver
Product specification
TDA8051
PINNING
SYMBOL
I_OUT
I_OUTC
I_OUT2
I_IN1
I_OUT1
A1VCC
DEMOD_IN
LNA_OUT
LNA_IN
A1GND
AGC_IN
OSC_IN
DVCC
CLK
DATA
EN
TEST
CP
TUNE
DGND
TKB
TKA
A2VCC
A2GND
A3VCC
OUTGND
OUTVCC
Q_OUT1
Q_IN1
Q_OUT2
Q_OUTC
Q_OUT
PIN
DESCRIPTION
1 I data buffered balanced output
2 I data buffered balanced output
3 I data filtered output
4 input to active filter amplifier for
I data
5 I data raw output
6 analog supply voltage 1
7 demodulator RF input
8 low noise amplifier RF output
9 low noise amplifier RF input
10 analog ground 1
11 AGC control voltage input
12 oscillator input
13 digital supply voltage
14 3-wire bus serial control clock
15 3-wire bus serial control data
16 3-wire bus serial control enable
(active LOW)
17 not connected
18 charge pump output for PLL loop
filter
19 tuning voltage output
20 digital ground
21 VCO tank circuit input
22 VCO tank circuit input
23 analog supply voltage 2
24 analog ground 2
25 analog supply voltage 3
26 output amplifiers ground
27 output amplifiers supply voltage
28 Q data raw output
29 input to active filter amplifier for
Q data
30 Q data filtered output
31 Q data buffered balanced output
32 Q data buffered balanced output
handbook, halfpage
I_OUT 1
I_OUTC 2
I_OUT2 3
I_IN1 4
I_OUT1 5
A1VCC 6
DEMOD_IN 7
LNA_OUT 8
LNA_IN 9
A1GND 10
AGC_IN 11
OSC_IN 12
DVCC 13
CLK 14
DATA 15
EN 16
32 Q_OUT
31 Q_OUTC
30 Q_OUT2
29 Q_IN1
28 Q_OUT1
27 OUTVCC
26 OUTGND
25 A3VCC
TDA8051
24 A2GND
23 A2VCC
22 TKA
21 TKB
20 DGND
19 TUNE
18 CP
17 TEST
FCE171
Fig.2 Pin configuration.
1999 Aug 20
4