TDA8051 Datasheet, PDF (10/24 Pages) NXP Semiconductors – QPSK receiver

Philips Semiconductors
QPSK receiver
Product specification
TDA8051
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX.
UNIT
3-wire bus
V_IL
input Low level
guaranteed by design
−
− 0.8
V
V_IH
input High level
guaranteed by design
2.4
−−
V
f_clk
clock frequency
guaranteed by design
−
330 −
kHz
t_su
input data to CLK set-up time guaranteed by design
−
2−
µs
t_h
input data to CLK hold time guaranteed by design
−
1−
µs
t_d(strt)
delay to rising clock edge
guaranteed by design
−
3−
µs
t_d(stp)
delay from last clock edge guaranteed by design
−
3−
µs
Notes
1. The frequency range of the receiver is 44 to 130 MHz. The local oscillator (LO) operates at twice the output
frequency (88 to 260 MHz). Frequency control by varicap diodes allows a variation over one octave.
2. Crystal oscillator. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is parallel
resonant with load capacitance of 18 to 20 pF. Connection to V_CC is preferred but can also be to GND.
Note to characteristics
handbook, full pagewidth
105 MHz
DEMOD_IN
+5 V
103 MHz
×
0¡ 90¡
×
I_OUT1
VCO 200 MHz
Q_OUT1
10 dB above max. input level
= 20 dBmVrms each tone
maximum
input
level
nominal
output level
= 22 dBmVrms
each tone
+10 dB = 32 dBmVrms each tone
IM3 _IM2
103
105
f (MHz)
12 3
5
7 _{f (MHz)}
FCE172
Fig.3 IM2 and IM3 measurement of the demodulator.
1999 Aug 20
10