74HCT573PW Datasheet, PDF (4/21 Pages) NXP Semiconductors – Octal D-type transparent latch 3-state

NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
74HC573
74HCT573
20 V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aae076
Fig 5. Pin configuration DIP20, SO20, SSOP20 and
TSSOP20
terminal 1
index area
74HC573
74HCT573
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND⁽¹⁾
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
001aae077
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input
Fig 6. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
LE
Q[0:7]
V_CC
Pin description
Pin
Description
1
3-state output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8, 9
data input
10
ground (0 V)
11
latch enable input (active HIGH)
19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
20
supply voltage
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 15 August 2012
© NXP B.V. 2012. All rights reserved.
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