 English |
|
|
|
|
|
|
|
| 74HCT573PW Datasheet, PDF (12/21 Pages) NXP Semiconductors – Octal D-type transparent latch 3-state | |||
| |||
| ◁ |
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
tW
VI 90 %
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 11. Test circuit for measuring switching times
Table 9. Test data
Type
Input
74HC573
74HCT573
VI
tr, tf
VCC
6 ns
3V
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 kï
1 kï
S1 position
tPHL, tPLH
open
open
tPZH, tPHZ
GND
GND
tPZL, tPLZ
VCC
VCC
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 â 15 August 2012
© NXP B.V. 2012. All rights reserved.
12 of 21
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese