74HCT573PW Datasheet, PDF (1/21 Pages) NXP Semiconductors – Octal D-type transparent latch 3-state

74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 5 — 15 August 2012
Product data sheet
1. General description
The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
no. 7A.
The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all latches.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are
transparent, i.e. a latch output changes state each time its corresponding D input
changes.
When LE is LOW the latches store the information that was present at the D-inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
The 74HC573; 74HCT573 is functionally identical to:
• 74HC563; 74HCT563, but inverted outputs
• 74HC373; 74HCT373, but different pin arrangement
2. Features and benefits
 Input levels:
 For 74HC573: CMOS level
 For 74HCT573: TTL level
 Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
 Useful as input or output port for microprocessors and microcomputers
 3-state non-inverting outputs for bus-oriented applications
 Common 3-state output enable input
 Multiple package options
 ESD protection:
 HBM JESD22-A114F exceeds 2 000 V
 MM JESD22-A115-A exceeds 200 V
 Specified from 40 C to +85 C and from 40 C to +125 C