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| 74HC73 Datasheet, PDF (4/21 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger | |||
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Philips Semiconductors
74HC73
Dual JK ï¬ip-ï¬op with reset; negative-edge trigger
C
C
C
C
K
Q
J
C
C
C
C
R
Q
CP
C
C
Fig 4. Logic diagram (one ï¬ip-ï¬op)
001aab982
6. Pinning information
6.1 Pinning
1CP 1
1R 2
1K 3
VCC 4
2CP 5
2R 6
2J 7
Fig 5. Pin conï¬guration
14 1J
13 1Q
12 1Q
73
11 GND
10 2K
9 2Q
8 2Q
001aab978
6.2 Pin description
Table 3:
Symbol
1CP
1R
1K
VCC
2CP
2R
2J
2Q
2Q
2K
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
Description
clock input for ï¬ip-ï¬op 1 (HIGH-to-LOW, edge-triggered)
asynchronous reset input for ï¬ip-ï¬op 1 (active LOW)
synchronous K input for ï¬ip-ï¬op 1
positive supply voltage
clock input for ï¬ip-ï¬op 2 (HIGH-to-LOW, edge-triggered)
asynchronous reset input for ï¬ip-ï¬op 2 (active LOW)
synchronous J input for ï¬ip-ï¬op 2
complement ï¬ip-ï¬op 2 output
true ï¬ip-ï¬op 2 output
synchronous K input for ï¬ip-ï¬op 2
9397 750 13815
Product data sheet
Rev. 03 â 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
4 of 21
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