74HC73 Datasheet, PDF (11/21 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger

Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics …continued
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF; see Figure 8.
Symbol Parameter
Conditions
t_su
set-up time nJ, nK to nCP
t_h
hold time nJ, nK to nCP
f_max
maximum clock frequency
T_amb = −40 °C to +125 °C
t_PHL, t_PLH propagation delay nCP to nQ
propagation delay nCP to nQ
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
propagation delay nR to nQ, nQ
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 7
t_THL, t_TLH
t_W
output transition time
nCP clock pulse width HIGH or LOW
nR reset pulse width HIGH or LOW
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 7
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
Min
Typ
Max Unit
100
-
-
ns
20
-
-
ns
17
-
-
ns
3
-
-
ns
3
-
-
ns
3
-
-
ns
4.8
-
-
MHz
24
-
-
MHz
28
-
-
MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
-
24
-
20
-
120
-
24
-
20
-
240
ns
48
ns
41
ns
240
ns
48
ns
41
ns
220
ns
44
ns
38
ns
110
ns
22
ns
19
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
9397 750 13815
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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