74HC73 Datasheet, PDF (10/21 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger

Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics …continued
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF; see Figure 8.
Symbol Parameter
Conditions
Min
Typ
Max Unit
t_h
hold time nJ, nK to nCP
see Figure 6
V_CC = 2.0 V
3
−8
-
V_CC = 4.5 V
3
−3
-
V_CC = 6.0 V
3
−2
-
f_max
maximum clock frequency
see Figure 6
V_CC = 2.0 V
6.0
23
-
V_CC = 4.5 V
30
70
-
V_CC = 6.0 V
35
83
-
V_CC = 5.0 V; C_L = 15 pF
-
77
-
C_PD
power dissipation capacitance per V_I = GND to V_CC
flip-flop
[1] _-
30
-
ns
ns
ns
MHz
MHz
MHz
MHz
pF
T_amb = −40 °C to +85 °C
t_PHL, t_PLH propagation delay nCP to nQ
propagation delay nCP to nQ
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
-
-
200
ns
-
-
40
ns
-
-
34
ns
propagation delay nR to nQ, nQ
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 7
-
-
200
ns
-
-
40
ns
-
-
34
ns
t_THL, t_TLH
t_W
output transition time
nCP clock pulse width HIGH or LOW
nR reset pulse width HIGH or LOW
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 7
-
-
-
-
-
-
-
-
-
-
-
-
100
-
20
-
17
-
180
ns
36
ns
31
ns
95
ns
19
ns
16
ns
-
ns
-
ns
-
ns
t_rem
removal time nR to nCP
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 7
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
100
-
-
ns
20
-
-
ns
17
-
-
ns
100
-
-
ns
20
-
-
ns
17
-
-
ns
9397 750 13815
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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