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| 74HC73 Datasheet, PDF (13/21 Pages) NXP Semiconductors – Dual JK flip-flop with reset; negative-edge trigger | |||
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Philips Semiconductors
12. Waveforms
74HC73
Dual JK ï¬ip-ï¬op with reset; negative-edge trigger
nJ, nK
input
nCP input
nQ output
nQ output
VM
tsu
th
tsu
1/f max
VM
tW
tPHL
VM
tTHL
VM
th
tPLH
tTLH
tTLH
tPLH
tTHL
tPHL
001aab983
Fig 6.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VM = 0.5 Ã VI.
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the
clock pulse width, the J and K to nCP set-up and hold times, the output transition
times and the maximum clock frequency
nCP input
nR input
tW
VM
tPHL
VM
trem
nQ output
tPLH
nQ input
001aab984
VM = 0.5 Ã VI.
Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays
and the reset pulse width and the nR to nCP removal time
9397 750 13815
Product data sheet
Rev. 03 â 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13 of 21
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