74F50728 Datasheet, PDF (4/12 Pages) NXP Semiconductors – Synchronizing cascaded dual positive edge-triggered D-type flip-flop

Philips Semiconductors
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
Product specification
74F50728
characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plug–in retrofitting of previously designed systems.
Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.
Having determined the T₀ and τ of the flop, calculating the mean
time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat different than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.
Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:
MTBF = e^(t’/t)/T_of_Cf_I
In this formula, f_C is the frequency of the clock, f_I is the average
input event frequency, and t’ is the period of the clock input (20
nanoseconds). In this situation the f_I will be twice the data
frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
greater than 10⁴¹ seconds. Using the above formula the actual
MTBF is 2.23 X 10⁴² seconds or about 7 X 10³⁴ years.
TYPICAL VALUES FOR τ AND T₀ AT VARIOUS V_CCS AND TEMPERATURES
T_amb = 0°C
T_amb = 25°C
V_CC = 5.5V
V_CC = 5.0V
V_CC = 4.5V
τ
125ps
115ps
115ps
T₀
1.0 X 10⁹ sec
1.3 X 10¹⁰ sec
3.4 X 10¹³ sec
τ
138ps
135ps
132ps
T₀
5.4 X 10⁶ sec
9.8 X 10⁶ sec
5.1 X 10⁸ sec
τ
160ps
167ps
175ps
T_amb = 70°C
T₀
1.7 X 10⁵ sec
3.9 X 10⁴ sec
7.3 X 10⁴ sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
10⁷⁰
10⁶⁰
Mean time
between failures
(seconds)
10⁵⁰
10⁴⁰
10³⁰
10²⁰
1 billion years
10¹⁰
10⁰⁰
NOTE: V_CC = 5V, T_amb = 25°C, τ =135ps, To = 9.8 X 10⁸ sec
Clock = 40MHz
Clock = 50MHz
Clock = 650MHz
Clock = 70MHz
Clock = 80MHz
Clock = 100MHz
1K
100K
Data frequency (Hz)
Figure 2.
10M
SF00610
September 14, 1990
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