74F50728 Datasheet, PDF (3/12 Pages) NXP Semiconductors – Synchronizing cascaded dual positive edge-triggered D-type flip-flop

Philips Semiconductors
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
Product specification
74F50728
PIN CONFIGURATION
RD0 ¹
D0 2
CP0 3
SD0 ⁴
Q0 5
Q0 6
GND 7
14 VCC
13 _RD1
12 D1
11 CP1
10 SD1
9 Q1
8 _Q1
SF00605
LOGIC SYMBOL
2 12
D0 D1
3
CP0
4
SD0
1
RD0
11
CP1
10
SD1
13
RD1
Q0 Q0 Q1 Q1
V_CC = Pin 14
GND = Pin 7
56 98
SF00606
IEC/IEEE SYMBOL
4
&
S
3
C1
2
1D
1
R
10
S
11
C2
12
2D
13
R
3
6
9
8
SF00607
LOGIC DIAGRAM
4, 10
SDn
2, 12
Dn
3, 11
CPn
1, 13
RDn
V_cc = Pin 14
GND = Pin 7
DQ
CP ^Q
D
Q ^{5, 9} _Qn
CP ^{Q 6, 8 Q n}
SF00608
NOTE: Data entering the flip–flop requires two clock cycles to
arrive at the output.
SYNCHRONIZING SOLUTIONS
Synchronizing incoming signals to a system clock has proven to be
costly, either in terms of time delays or hardware. The reason for this
is that in order to synchronize the signals a flip–flop must be used to
”capture” the incoming signal. While this is perhaps the only way to
synchronize a signal, to this point, there have been problems with
this method. Whenever the flop’s setup or hold times are violated
the flop can enter a metastable state causing the outputs in turn to
glitch, oscillate, enter an intermediate state or change state in some
abnormal fashion. Any of these conditions could be responsible for
causing a system crash. To minimize this risk, flip–flops are often
cascaded so that the input signal is captured on the first clock pulse
and released on the second clock pulse (see Fig.1). This gives the
first flop about one clock period minus the flop delay and minus the
second flop’s clock–to–Q setup time to resolve any metastable
condition. This method greatly reduces the probability of the outputs
of the synchronizing device displaying an abnormal state but the
trade-off is that one clock cycle is lost to synchronize the incoming
data and two separate flip–flops are required to produce the
cascaded flop circuit. In order to assist the designer of synchronizing
circuits Philips Semiconductors is offering the 74F50728.
DATA
CLOCK
DQ
CP ^Q
DQ
CP ^Q
Q OUTPUT
Q OUTPUT
SF00609
Figure 1.
The 50728 consists of two pair of cascaded D–type flip–flops with
metastable immune features and is pin compatible with the 74F74.
Because the flops are cascaded on a single part the metastability
September 14, 1990
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