74F50728 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Synchronizing cascaded dual positive edge-triggered D-type flip-flop

Philips Semiconductors
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
Product specification
74F50728
FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• See 74F5074 for synchronizing dual D-type flip-flop
• See 74F50109 for synchronizing dual J–K positive edge-triggered
flip-flop
• See 74F50729 for synchronizing dual dual D-type flip-flop with
edge-triggered set and reset
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F50728 is a cascaded dual positive edge–triggered D–type
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. They set and reset
both flip–flops of a cascaded pair simultaneously. Data must be
stable just one setup time prior to the low–to–high transition of the
clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output. Data entering the 74F50728 requires two
clock cycles to arrive at the outputs.
The 74F50728 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50728
are: τ ≅ 135ps and T₀ ≅ 9.8 X 10⁶ sec where τ represents a
function of the rate at which a latch in a metastable state resolves
that condition and T_o represents a function of the measurement of
the propensity of a latch to enter a metastable state.
TYPE
74F50728
TYPICAL f_max
145 MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
23mA
ORDERING INFORMATION
DESCRIPTION
14–pin plastic DIP
14–pin plastic SO
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
N74F50728N
N74F50728D
ORDER CODE
INDUSTRIAL RANGE
V_CC = 5V ±10%,
T_amb = –40°C to +85°C
I74F50728N
I74F50728D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
D0, D1
Data inputs
1.0/0.417
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
SD0, SD1
Set inputs (active low)
1.0/1.0
RD0, RD1
Reset inputs (active low)
1.0/1.0
Q0, Q1, Q0, Q1
Data outputs
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
50/33
LOAD VALUE HIGH/
LOW
20µA/250µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
September 14, 1990
2
853-1389 00421