74AUP2G00 Datasheet, PDF (4/16 Pages) NXP Semiconductors – Low-power dual 2-input NAND gate

Philips Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V_CC
I_IK
V_I
I_OK
V_O
I_O
I_CC
I_GND
T_stg
P_tot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
V_I < 0 V
V_O < 0 V
Active mode and Power-down mode
V_O = 0 V to V_CC
T_amb = −40 °C to +125 °C
−0.5
-
[1] _−0.5
-
[1] _−0.5
-
-
-
−65
[2] _-
+4.6
V
−50
mA
+4.6
V
−50
mA
+4.6
V
±20
mA
+50
mA
−50
mA
+150
°C
250
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 °C the value of P_tot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 45 °C the value of P_tot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V_CC
V_I
V_O
T_amb
∆t/∆V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
Active mode
ambient temperature
Power-down mode; V_CC = 0 V
input transition rise and fall rate V_CC = 0.8 V to 3.6 V
Min Max Unit
0.8
3.6
V
0
3.6
V
0
V_CC
V
0
3.6
V
−40 +125 °C
0
200 ns/V
74AUP2G00_1
Product data sheet
Rev. 01 — 25 August 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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