74AUP2G00 Datasheet, PDF (3/16 Pages) NXP Semiconductors – Low-power dual 2-input NAND gate

Philips Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
74AUP2G00
1A 1
8 V_CC
1B 2
7 1Y
2Y 3
6 2B
GND 4
5 2A
001aae363
Transparent top view
Fig 5. Pin configuration SOT833-1 (XSON8)
6.2 Pin description
Table 3.
Symbol
1A
1B
2Y
GND
2A
2B
1Y
V_CC
Pin description
Pin
SOT765-1 and SOT833-1
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
7. Functional description
Table 4. Function table^[1]
Input
nA
nB
L
L
L
H
H
L
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
terminal 1
index area
74AUP2G00
1Y 1
7 1A
2B 2
6 1B
2A 3
5 2Y
001aae364
Transparent top view
Fig 6. Pin configuration SOT902-1 (XQFN8)
Description
data input 1A
data input 1B
data output 2Y
ground (0 V)
data input 2A
data input 2B
data output 1Y
supply voltage
Output
nY
H
H
H
L
74AUP2G00_1
Product data sheet
Rev. 01 — 25 August 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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