74AUP2G00 Datasheet, PDF (2/16 Pages) NXP Semiconductors – Low-power dual 2-input NAND gate

Philips Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G00DC −40 °C to +125 °C VSSOP8
74AUP2G00GT −40 °C to +125 °C XSON8
74AUP2G00GM −40 °C to +125 °C XQFN8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package; no leads; 8 SOT902-1
terminals; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP2G00DC
74AUP2G00GT
74AUP2G00GM
5. Functional diagram
Marking code
p00
p00
p00
1 1A
2 1B
5 2A
6 2B
1Y 7
2Y 3
mna712
Fig 1. Logic symbol
1
&
7
2
5
&
3
6
mna713
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
B
Y
A
mna099
Fig 3. Logic diagram (one gate)
74AUP2G00
1A 1
1B 2
2Y 3
GND 4
8 V_CC
7 1Y
6 2B
5 2A
001aae362
Fig 4. Pin configuration SOT765-1 (VSSOP8)
74AUP2G00_1
Product data sheet
Rev. 01 — 25 August 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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