74AUP2G00 Datasheet, PDF (14/16 Pages) NXP Semiconductors – Low-power dual 2-input NAND gate

Philips Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
74AUP2G00_1
20060825
Data sheet status
Product data sheet
Change notice
-
Supersedes
-
74AUP2G00_1
Product data sheet
Rev. 01 — 25 August 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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