74HC7046A Datasheet, PDF (35/38 Pages) NXP Semiconductors – Phase-locked-loop with lock detector

Philips Semiconductors
Phase-locked-loop with lock detector
Product specification
74HC/HCT7046A
The maximum permitted phase error
must be defined, before t_LD can be
defined using the following formula:
t_LD = ^φ--3--^m-6---^a_0---^x × -f-1_I--_N-- .
Using this calculated value in Fig.32,
it is possible to define the value of
C_LD, e.g. assuming the phase error is
36° and f_IN = 2 MHz:
t_LD = _{3-3---66---0-}^°- × _{2------M--1---H----z--} = 50 ns,
and using Fig.32, it can be seen that
C_LD is 26 pF.
With the addition of one retriggerable
monostable (e.g. “123”, “423” or
“4538”) a steady state LOW and
HIGH indication can be obtained, as
shown in Fig.33.
Fig.33 Steady state signal for lock indication.
December 1990
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