74HC7046A Datasheet, PDF (3/38 Pages) NXP Semiconductors – Phase-locked-loop with lock detector

Philips Semiconductors
Phase-locked-loop with lock detector
Product specification
74HC/HCT7046A
waveforms for the PC1 loop locked at
f_o are shown in Fig.7.
The frequency capture range (2f_c) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2f_L) is defined
as the frequency range of input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration retains lock
even with very noisy input signals.
Typical behaviour of this type of
phase comparator is that it can lock to
input frequencies close to the
harmonics of the VCO centre
frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIG_IN and COMP_IN are not important.
PC2 comprises two D-type flip-flops,
control-gating and a 3-state output
stage. The circuit functions as an
up-down counter (Fig.5) where SIG_IN
causes an up-count and COMP_IN a
down-count. The transfer function of
PC2, assuming ripple (f_r = f_i) is
suppressed,
is:
V_DEMOUT = ^V--4---C-_π--^C-- ( φ_SIGIN – φ_COMPIN)
where V_DEMOUT is the demodulator
output at pin 10;
V_DEMOUT = V_PC2OUT (via low-pass
filter).
The phase comparator gain is:
K_p = -V-4---^C-_π--^C-- (V ⁄ r) .
V_DEMOUT is the resultant of the initial
phase differences of SIG_IN and
COMP_IN as shown in Fig.8. Typical
waveforms for the PC2 loop locked at
f_o are shown in Fig.9.
When the frequencies of SIG_IN and
COMP_IN are equal but the phase of
SIG_IN leads that of COMP_IN, the
p-type output driver at PC2_OUT is held
“ON” for a time corresponding to the
phase difference (φ_DEMOUT). When
the phase of SIG_IN lags that of
COMP_IN, the n-type driver is held
“ON”.
When the frequency of SIG_IN is higher
than that of COMP_IN, the p-type
output driver is held “ON” for most of
the input signal cycle time, and for
the remainder of the cycle both n and
p- type drivers are “OFF” (3-state). If
the SIG_IN frequency is lower than the
COMP_IN frequency, then it is the
n-type driver that is held “ON” for
most of the cycle. Subsequently, the
voltage at the capacitor (C2) of the
low-pass filter connected to PC2_OUT
varies until the signal and comparator
inputs are equal in both phase and
frequency. At this stable point the
voltage on C2 remains constant as
the PC2 output is in 3-state and the
VCO input at pin 9 is a high
impedance.
Thus, for PC2, no phase difference
exists between SIG_IN and COMP_IN
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both p and n-type
drivers are “OFF” for most of the
signal input cycle. It should be noted
that the PLL lock range for this type of
phase comparator is equal to the
capture range and is independent of
the low-pass filter. With no signal
present at SIG_IN the VCO adjusts, via
PC2, to its lowest frequency.
APPLICATIONS
• FM modulation and demodulation
• Frequency synthesis and
multiplication
• Frequency discrimination
• Tone decoding
• Data synchronization and
conditioning
• Voltage-to-frequency conversion
• Motor-speed control
December 1990
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