PHN103 Datasheet, PDF (3/12 Pages) NXP Semiconductors – N-channel enhancement mode MOS transistor

Philips Semiconductors
N-channel enhancement mode
MOS transistor
Product specification
PHN103
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V_DS
V_GS
I_D
I_DM
P_tot
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
T_stg
storage temperature
T_j
operating junction temperature
Source-drain diode
I_S
source current (DC)
I_SM
peak pulsed source current
CONDITIONS
T_s = 80 °C; note 1
note 2
T_s = 80 °C
T_amb = 25 °C; note 3
T_amb = 25 °C; note 4
MIN.
−
−
−
−
−
−
−
−65
−65
MAX.
30
±20
8.5
35
4
2.7
1.15
+150
+150
T_s = 80 °C
note 2
−
5
−
20
Notes
1. T_s is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Device mounted on printed-circuit board with an R_{th a-tp} (ambient to tie-point) of 27.5 K/W.
4. Device mounted on printed-circuit board with an R_{th a-tp} (ambient to tie-point) of 90 K/W.
UNIT
V
V
A
A
W
W
W
°C
°C
A
A
THERMAL CHARACTERISTICS
SYMBOL
R_{th j-s}
PARAMETER
thermal resistance from junction to soldering point
VALUE
17.5
UNIT
K/W
1997 Jun 20
3