PHN1011 Datasheet, PDF (3/7 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHN1011
Normalised Power Derating, Ptot (%)
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100 120 140 160
Ambient temperature, Ta (C)
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_a)
Normalised Current Derating, ID (%)
120
100
80
60
40
20
0
0
20
40
60
80
100 120 140 160
Ambient temperature, Ta (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_a); conditions: V_GS ≥ 5 V
100 ^{Peak Pulsed Drain Current, IDM (A)}
RDS(on) = VDS/ ID
10
1
D.C.
0.1
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.01
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.3. Safe operating area. T_a = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Transient thermal impedance, Zth j-mb (K/W)
100
D = 0.5
0.2
10
0.1
0.05
0.02
1
P
D
0.1 ^{single pulse}
D = tp/T
tp
0.01
1E-06
1E-05
1E-04
1E-03 1E-02
Pulse width, tp (s)
T
1E-01 1E+00
1E+01
Fig.4. Transient thermal impedance.
Z_{th j-a} = f(t); parameter D = t_p/T
Drain Current, ID (A)
50
VGS = 10 V ^{5 V}
45
4.5 V
40
Tj = 25 C
3V
35
2.8 V
30
25
2.6 V
20
15
10
5
0
0
2.4 V
2.2 V
2V
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Drain-Source Voltage, VDS (V)
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
2.2 V 2.4 V
2.6 V
0.09
Tj = 25 C
0.08
0.07
2.8V
0.06
0.05
3V
0.04
0.03
0.02
0.01
0
0
5V
VGS =4.5 V
10V
5
10 15 20 25 30 35 40 45 50
Drain Current, ID (A)
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
June 1999
3
Rev 1.100