PHN1011 Datasheet, PDF (1/7 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHN1011
FEATURES
SYMBOL
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low-profile surface mount
package
• Logic level compatible
d
g
s
QUICK REFERENCE DATA
V_DSS = 25 V
I_D = 11 A
R_DS(ON) ≤ 11 mΩ (V_GS = 10 V)
R_DS(ON) ≤ 13.5 mΩ (V_GS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a surface mounting
plastic package using ’trench’
technology. The combination of
very low on-state resistance and
low switching losses make this
device the optimum choice in high
speed computer motherboard d.c.
to d.c. converters.
The PHN1011 is supplied in the
SOT96-1 (SO8) surface mounting
package
PINNING
PIN
DESCRIPTION
1-3 source
4 gate
5-8 drain
SOT96-1 (SO8)
876 5
pin 1 index
123 4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DSS
V_DGR
V_GS
V_GSM
I_D
I_DM
P_tot
T_j, T_stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse peak
value)
Drain current (t_p ≤ 10 s)
Drain current (pulse peak value)
Total power dissipation
Operating junction and storage
temperature
T_j = 25 ˚C to 150˚C
T_j = 25 ˚C to 150˚C;
R_GS = 20 kΩ
-
T_a = 25 ˚C
T_a = 70 ˚C
T_a = 25 ˚C
T_a = 25 ˚C
T_a = 70 ˚C
-
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
11
9
44
2.5
1.6
150
UNIT
V
V
V
V
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
R_{th j-a}
R_{th j-a}
Thermal resistance junction
to ambient
Thermal resistance junction
to ambient
CONDITIONS
Surface mounted, FR4 board, t ≤ 10 sec
Surface mounted, FR4 board
TYP.
-
150
MAX.
50
-
UNIT
K/W
K/W
June 1999
1
Rev 1.100