TDA8752 Datasheet, PDF (29/36 Pages) NXP Semiconductors – Triple high speed Analog-to-Digital Converter ADC

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Table 13 Examples of PLL settings and performances; note 1
VIDEO
STANDARDS
CGA: 640 × 200
VGA: 640 × 480
VESA: 800 × 600
VESA: 1024 × 768
SUN: 1152 × 900
f_ref (kHz)
f_CLK
(MHz)
15.75 14.3
31.5 25.2
48.08 50
60.02 78.8
66.67 100
N
912
800
1 040
1 312
1 500
KO
(MHz/V)
15
30
60
100
100
CZ
(nF)
CP
(nF)
I_P (µA)
Z
(kΩ)
LONG TIME JITTER⁽²⁾
ps (RMS) ns (p-p)
150 1 200 4
−
−
150 1 400 2
610
3.6
150 1 700 1
480
2.9
150 1 700 1
380
2.3
150 1 700 1
360
2.2
PLL PHASE
DRIFT⁽³⁾ (ns)
1.2
0.7
0.55
0.3
0.3
Notes
1. Values measured at V_CCA = V_DDD = V_CCD = V_CCO = 5 V and T_amb = 25°C.
2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.
3. Measured between 0 and 70 °C.