TDA8752 Datasheet, PDF (25/36 Pages) NXP Semiconductors – Triple high speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
t_COASTmax
t_recap
t_cap
Φ_step
maximum coast mode time
PLL recapture time
PLL capture time
phase shift step
−
when coast mode is aborted −
in start-up conditions
−
T_amb = 25 °C
−
−
3
−
11.25
ADCs
f_s
INL
DNL
ENOB
maximum sampling frequency TDA8752/6
60
−
TDA8752/8
100 −
DC integral non linearity
from IC analog input to
−
±0.5
digital output; ramp input;
f_CLK = 100 MHz
DC differential non linearity from IC analog input to
−
±0.5
digital output; ramp input;
f_CLK = 100 MHz
effective number of bits
from IC analog input to
−
7.4
digital output; 10 kHz sine
wave input; ramp input;
f_CLK = 100 MHz; note 1
Signal-to-noise ratio
S/N
signal-to-noise ratio
maximum gain;
f_CLK = 100 MHz
minimum gain;
f_CLK = 100 MHz
−
45
−
44
Spurious free dynamic range
SFDR
spurious free dynamic range
maximum gain;
f_CLK = 100 MHz
minimum gain;
f_CLK = 100 MHz
−
60
−
60
Clock timing output (CKADCO, CKBO and CKAO)
η_ext
f_CLK(max)
ADC clock duty cycle
maximum clock frequency
100 MHz output
45
50
100 −
Clock timing input (CKEXT)
f_CLK(max)
t_CPH
t_CPL
t_d(CLKO)
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
delay from CKEXT to
CKADCO
INV set to LOW
INV set to HIGH
100 −
3.6 −
4.5 −
13.6 14.7
−
-t-^C--2--^L--^K--
∆t_sample
time difference between
samples
operating in the same supply −
0.1
and temperature condition
MAX.
40
−
5
−
UNIT
lines
lines
ms
deg
−
MHz
−
MHz
±1.5
LSB
±1.0
LSB
−
bits
−
dB
−
dB
−
dB
−
dB
55
%
−
MHz
−
MHz
−
ns
−
ns
15.2 ns
−
ns
0.3
ns
1999 Mar 09
25