TDA8752 Datasheet, PDF (12/36 Pages) NXP Semiconductors – Triple high speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752
Phase-locked loop
The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT. Selection
is performed via the serial interface bus.
The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency
100 MHz for the TDA8752/8 and 60 MHz for the
TDA8752/6. The gain of the VCO part can be controlled via
the serial interface, depending on the frequency range to
which the PLL is locked.
To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the frequency and
the current is given by the following equation:
f_n = _2--1--π-- --₍--C-----_z---K--₊--^O---C-I--^P-_P-----₎----N--
Where:
f_n = the natural PLL frequency
K_O = the VCO gain
N = the division number
C_z and C_P = capacitors of the PLL filter.
The other PLL equation is as follows:
f_z
=
2----π^-----×^{-----R1------}×^-----C----_z^-
and

ξ

=
12--
×
-ff-ⁿ-_z



Where:
f_z = loop filter zero frequency
R = the chosen resistance for the filter
ξ = the damping factor.
Different resistances for the filter can be programmed via
the serial interface. To have better performances, the PLL
parameters should be chosen so that:
f_n/f_ref ≅ 0.05
ξ ≅ 1.5.
It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752).
For this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25° each on the whole
PLL frequency range).
CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO (LOW during 8 clock
periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO
and CKADCO. The timing is given in Fig.5.
andbook, full pagewidth
CKREF
CKAO
CKREFO
tCKAO
tCKREFO
t_CKAO = t_CLK(buffer) + t_{phase selector} (t_CLK(buffer) = 10 ns and t_{phase selector} = -t-^p---^h--^a---^s--^e-2---^s_π--^e---^l-^e--^c--^t--^o--^r × T_CLK(pixel)).
t_CKREFO = either t_CKAO if phase A ≥01000 or t_CKAO + T_CLK(pixel) if phase A <01000.
Fig.5 Timing.
1999 Mar 09
12
MBK773