TDA8752 Datasheet, PDF (26/36 Pages) NXP Semiconductors – Triple high speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752
SYMBOL
PARAMETER
CONDITIONS
Data timing (see Fig.11); f_CLK = 100 MHz; C_L = 10 pF; note 2
t_d(s)
sampling delay time
t_d(o)
output delay time
t_h(o)
output hold time
referenced to CKADCO
3-state output delay time; (see Fig.12)
t_dZH
output enable HIGH
t_dZL
output enable LOW
t_dHZ
output disable HIGH
t_dLZ
output disable LOW
PLL clock output
V_OL
LOW-level output voltage
I_o = 1 mA
V_OH
HIGH-level output voltage
I_o = − 1 mA
I_OL
LOW-level output current
V_OL = 0.4 V
I_OH
HIGH-level output current
V_OH = 2.7 V
ADC data outputs
V_OL
LOW-level output voltage
I_o = 1 mA
V_OH
HIGH-level output voltage
I_o = − 1 mA
I_OL
LOW-level output current
V_OL = 0.4 V
I_OH
HIGH-level output current
V_OH = 2.7 V
TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)
V_IL
LOW level input voltage
V_IH
HIGH level input voltage
I_IL
LOW level input current
V_IL = 0.4 V
I_IH
HIGH level input current
V_IH = 2.7 V
Z_i
input impedance
C_i
input capacitance
3-wire serial bus
t_reset
t_su
t_h
reset time of the chip before
3-wire communication
data set-up time
data hold time
I²C-bus; see note 3
f_SCL
clock frequency
t_BUF
time the bus must be free
before new transmission can
start
MIN.
TYP.
MAX. UNIT
−
−
−
−3.3
4.6 5.5
−
ns
−2.6
ns
−
ns
−
12
−
10
−
50
−
65
−
ns
−
ns
−
ns
−
ns
−
0.3
2.4 3.5
−
2
−
−0.4
0.8
V
−
V
−
mA
−
mA
−
0
2.4
V_CCD
−
2
−
−0.5
0.8
V
−
V
−
mA
−
mA
−
−
2.0 −
400 −
−
−
−
4
−
4.5
0.8
V
−
V
−
µA
100
µA
−
kΩ
−
pF
−
600
−
100
−
100
−
ns
−
ns
−
ns
0
−
4.7 −
100
kHz
−
µs
1999 Mar 09
26