PDIUSBD12 Datasheet, PDF (25/35 Pages) NXP Semiconductors – USB interface device with parallel bus

Philips Semiconductors
PDIUSBD12
USB interface device with parallel bus
Table 17: AC characteristics (parallel interface)
Symbol Parameter
ALE timings
t_LH
ALE HIGH pulse width
t_AVLL
address valid to ALE LOW time
t_LLAX
ALE LOW to Address transition time
Write timings
t_CLWL
t_WHCH
t_AVWL
CS_N (DMACK_N) LOW to WR_N LOW time
WR_N HIGH to CS_N (DMACK_N) HIGH time
A0 Valid to WR_N LOW time
Conditions
t_WHAX
WR_N HIGH to A0 transition time
t_WL
WR_N LOW pulse width
t_WDSU
t_WDH
write data setup time
write data hold time
t_WC
write cycle time
t_{(WC - WD)} write command to write data
Read timings
t_CLRL
CS_N (DMACK_N) LOW to RD_N LOW time
t_RHCH
t_AVRL
t_RL
t_RLDD
t_RHDZ
t_RC
t_{(WC - RD)}
RD_N HIGH to CS_N (DMACK_N) HIGH time
A0 Valid to RD_N LOW time
RD_N LOW pulse width
RD_N LOW to Data Driven time
RD_N HIGH to Data Hi-Z time
read cycle time
write command to read data
[1] Can be negative.
[2] For DMA access only on the module 64^th byte and the second last (EOT-1)byte.
[3] The t_WC and t_RC timings are valid for back-to-back data access only.
Min
Max Unit
20
−
ns
10
−
ns
−
10
ns
0 ^[1]
−
ns
5
−
ns
0 ^[1]
−
ns
130^[2] -
ns
5
−
ns
20
−
ns
30
−
ns
10
−
ns
500^[3] −
ns
600
-
ns
0 ^[1]
−
ns
130^[2] -
ns
5
−
ns
0 ^[1]
−
ns
20
−
ns
−
20
ns
−
20
ns
500^[3] −
ns
600
-
ns
Fig 17. ALE timing.
9397 750 09238
Product data
Rev. 08 — 20 December 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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