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PR31500 Datasheet, PDF (22/24 Pages) NXP Semiconductors – Poseidon embedded processor
Philips Semiconductors
Poseidon embedded processor
Preliminary specification
MIPS
PR31500
POWER
Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF
ITEM
PARAMETER
1
VSTANDBY to /PON Rising
2
VSTANDBY to ONBUTN delay time
POWER TIMING DIAGRAM
RISING/FALLING
–
–
VSTANDBY
/PON
ONBUTN
1
2
Figure 14.
LIMITS
MIN
MAX
50
–
2
–
UNIT
ns
s
SN00181
CPU RESET
Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF
ITEM
PARAMETER
1
/CPURES low time
RISING/FALLING
–
LIMITS
MIN
MAX
10
–
UNIT
ns
/CPURES
1
Figure 15.
SN00182
1996 Sep 24
22