PR31500 Datasheet, PDF (2/24 Pages) NXP Semiconductors – Poseidon embedded processor

Philips Semiconductors
Poseidon embedded processor
Version 0.1
GENERAL DESCRIPTION
PR31500 Processor is a single-chip, low-cost, integrated embedded
processor consisting of MIPS R3000 core and system support logic
to interface with various types of devices.
PR31500 consists of a MIPS R3000 RISC CPU with 4 KBytes of
instruction cache memory and 1 KByte of data cache memory, plus
integrated functions for interfacing to numerous system components
and external I/O modules. The R3000 RISC CPU is also augmented
with a multiply/accumulate module to allow integrated DSP
functions, such as a software modem for high-performance standard
data and fax protocols.
The PR31500 processor can support both Little and Big Endian
operating systems. In addition the PR31500 provides a memory
management unit with an on-chip Translation Look aside Buffer
(TLB) for very fast virtual to physical address translation.
PR31500 also contains multiple DMA channels and a
high-performance and flexible Bus Interface Unit (BIU) for providing
an efficient means for transferring data between external system
memory, cache memory, the CPU core, and external I/O modules.
The types of external memory devices supported include dynamic
random access memory (DRAM), synchronous dynamic random
access memory (SDRAM), static random access memory (SRAM),
Flash memory, read-only memory (ROM), and expansion cards
(e.g., PCMCIA). PR31500 also contains a System Interface Module
(SIM) containing integrated functions for interfacing to numerous
external I/O modules such as liquid crystal displays (LCDs), the
UCB1100 (which handles most of the analog functions of the
system, including sound and telecom codecs and touchscreen
ADC), ISDN/high-speed serial, infrared, wireless peripherals, etc.
Lastly, PR31500 contains support for implementation of power
management, whereby various PR31500 internal modules and
external subsystems can be individually (under software control)
powered up and down.
Figure 1 shows an External Block Diagram of PR31500.
Preliminary specification
MIPS
PR31500
FEATURES
• 32-bit R3000 RISC static CMOS CPU
• 4 KByte instruction cache
• 1 KByte data cache
• Multiply/accumulator Instruction
• R3000A memory management unit with on-chip TLB
• Supports Big/Little Endian operating systems
• On-chip peripherals with individual power-down
– Multi-channel DMA controller
– Bus interface unit
– Memory controller for ROM, Flash, RAM, DRAM, SDRAM,
SRAM, and PCMCIA
– Power management module
– Video module
– Real-time clock 32.760KHz reference
– High-speed serial interface
– Infrared module
– Dual-UART
– SPI bus
• 3.3V supply voltage
• 208-pin LQFP (Low profile quad flat pack)
• 40MHz operation frequency
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE (°C) AND PACKAGE
PR31500ABC
0 to +70, 208-pin Low Profile Quad Flat Pack
FREQUENCY
(MHz)
40
DRAWING NUMBER
LQFP208
1996 Sep 24
2