74HC4024N Datasheet, PDF (2/18 Pages) NXP Semiconductors – 7-stage binary ripple counter

Philips Semiconductors
74HC4024
7-stage binary ripple counter
4. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns.
Symbol Parameter
Conditions
Min Typ
t_PHL, t_PLH
propagation delay CP to C_L = 15 pF;
Q0
V_CC = 5 V
-
14
f_max
maximum clock frequency C_L = 15 pF;
-
90
V_CC = 5 V
C_I
input capacitance
-
3.5
C_PD
power dissipation
V_I = GND to V_CC ^[1] -
25
capacitance
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + ∑(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in V;
N = number of inputs switching;
∑(C_L × V_CC2 × f_o) = sum of outputs.
5. Ordering information
Max Unit
-
ns
-
MHz
-
pF
-
pF
Table 2: Ordering information
Type number Package
Temperature range
74HC4024N
−40 °C to +125 °C
74HC4024D
−40 °C to +125 °C
74HC4024DB −40 °C to +125 °C
74HC4024PW −40 °C to +125 °C
Name
DIP14
SO14
SSOP14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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