74HC4024N Datasheet, PDF (11/18 Pages) NXP Semiconductors – 7-stage binary ripple counter

Philips Semiconductors
13. Waveforms
74HC4024
7-stage binary ripple counter
MR input
V_M
t_W
CP input
t_PHL
Q0 or Qn
output
1/f_max
t_rem
t_W
t_PLH
t_TLH
V_M
t_PHL
V_M
t_THL
001aab910
Fig 6.
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) removal time.
V_M = 0.5 × V_I.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock
pulse width, the output transition times and the maximum clock frequency
PULSE
V_I
GENERATOR
V_CC
V_O
D.U.T.
R_T
C_L
mna101
Fig 7.
Test data is given in Table 9.
Definitions for test circuit:
R_T = Termination resistance should be equal to output impedance Z_o of the pulse generator.
C_L = Load capacitance including jig and probe capacitance.
Load circuitry for switching times
Table 9:
Supply
V_CC
2.0 V
4.5 V
6.0 V
5.0 V
Test data
Input
V_I
V_CC
V_CC
V_CC
V_CC
t_r, t_f
6 ns
6 ns
6 ns
6 ns
Load
C_L
50 pF
50 pF
50 pF
15 pF
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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