74HC4024N Datasheet, PDF (10/18 Pages) NXP Semiconductors – 7-stage binary ripple counter

Philips Semiconductors
74HC4024
7-stage binary ripple counter
Table 8: Dynamic characteristics …continued
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF; see Figure 7.
Symbol Parameter
Conditions
T_amb = −40 °C to +125 °C
t_PHL, t_PLH propagation delay CP to Q0
propagation delay Qn to Qn+1
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
t_PHL
propagation delay MR to Q0
t_THL, t_TLH output transition time
t_W
CP clock pulse width HIGH or
LOW
MR master reset pulse width
HIGH
t_rem
removal time MR to CP
f_max
maximum clock frequency
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 6
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + ∑(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in V;
N = number of inputs switching;
∑(C_L × V_CC2 × f_o) = sum of outputs.
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
Min
Typ
Max
Unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
-
24
-
20
-
120
-
24
-
20
-
75
-
15
-
13
-
4.0
-
20
-
24
-
265
ns
53
ns
45
ns
120
ns
24
ns
20
ns
300
ns
60
ns
51
ns
110
ns
22
ns
19
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
MHz
-
MHz
-
MHz
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10 of 18