74HC40103DB Datasheet, PDF (2/25 Pages) NXP Semiconductors – 8-bit synchronous binary down counter

Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
2. Features
s Cascadable
s Synchronous or asynchronous preset
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Applications
s Divide-by-n counters
s Programmable timers
s Interrupt timers
s Cycle/program counters.
4. Quick reference data
Table 1: Quick reference data
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns.
Symbol
Parameter
Conditions
Min Typ Max Unit
t_PHL, t_PLH
propagation delay CP to TC C_L = 15 pF;
V_CC = 5 V
-
30 -
ns
f_max
maximum clock frequency C_L = 15 pF;
V_CC = 5 V
-
32 -
MHz
C_I
input capacitance
C_PD
power dissipation
capacitance
-
3.5 -
pF
V_I = GND to V_CC ^[1] -
24 -
pF
[1] C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i × N + ∑(C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in V;
N = number of inputs switching;
∑(C_L × V_CC2 × f_o) = sum of outputs.
9397 750 13812
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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