74HC40103DB Datasheet, PDF (11/25 Pages) NXP Semiconductors – 8-bit synchronous binary down counter

Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
Table 8: Dynamic characteristics …continued
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF; see Figure 13.
Symbol Parameter
Conditions
t_W
CP clock pulse width HIGH or see Figure 7
LOW
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
MR master reset pulse width
LOW
see Figure 9
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
PL preset enable pulse width
LOW
see Figure 9
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
t_rem
removal time MR to CP, PL to CP see Figure 10
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
t_su
set-up time PE to CP
see Figure 11
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
set-up time TE to CP
see Figure 12
set-up time Pn to CP
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 11
t_h
hold time PE to CP
hold time TE to CP
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 11
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 12
hold time Pn to CP
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
see Figure 11
V_CC = 2.0 V
V_CC = 4.5 V
V_CC = 6.0 V
9397 750 13812
Product data sheet
Rev. 03 — 12 November 2004
Min
Typ
Max
Unit
165
22
-
ns
33
8
-
ns
28
6
-
ns
125
39
-
ns
25
14
-
ns
21
11
-
ns
125
33
-
ns
25
12
-
ns
21
10
-
ns
50
14
-
ns
10
5
-
ns
9
4
-
ns
75
22
-
ns
15
8
-
ns
13
6
-
ns
150
44
-
ns
30
16
-
ns
26
13
-
ns
75
22
-
ns
15
8
-
ns
13
6
-
ns
0
−14
-
ns
0
−5
-
ns
0
−4
-
ns
0
−30
-
ns
0
−11
-
ns
0
−9
-
ns
0
−17
-
ns
0
−6
-
ns
0
−5
-
ns
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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