74HC40103DB Datasheet, PDF (17/25 Pages) NXP Semiconductors – 8-bit synchronous binary down counter

Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
P0 to P7
input
PE input
V_{M stable}
t_su
t_h
V_M
CP input
t_su
t_h
V_M
001aab931
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
V_M = 0.5 × V_I.
Fig 11. Waveforms showing hold and set-up times for
Pn, PE to CP
TE or PE
input
V_M
CP input
t_su
t_h
V_M
V_M = 0.5 × V_I.
001aab930
Fig 12. Waveforms showing hold and set-up times for
MR or PE to CP
PULSE
V_I
GENERATOR
V_CC
V_O
D.U.T.
R_T
C_L
mna101
Test data is given in Table 9.
Definitions for test circuit:
R_T = Termination resistance should be equal to output impedance Z_o of the pulse generator.
C_L = Load capacitance including jig and probe capacitance.
Fig 13. Load circuitry for switching times
Table 9:
Supply
V_CC
2.0 V
4.5 V
6.0 V
5.0 V
Test data
Input
V_I
V_CC
V_CC
V_CC
V_CC
t_r, t_f
6 ns
6 ns
6 ns
6 ns
Load
C_L
50 pF
50 pF
50 pF
15 pF
9397 750 13812
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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