TDA8924 Datasheet, PDF (15/35 Pages) NXP Semiconductors – 2 x 120 W class-D power amplifier

Philips Semiconductors
2 × 120 W class-D power amplifier
Objective specification
TDA8924
16 APPLICATION INFORMATION
16.1 BTL application
When using the power amplifier in a mono BTL application
(for more output power), the inputs of both channels must
be connected in parallel; the phase of one of the inputs
must be inverted; see Fig.5. In principle the loudspeaker
can be connected between the outputs of the two
single-ended demodulation filters.
16.2 Pin MODE
For correct operation the switching voltage at pin MODE
should be debounced. If pin MODE is driven by a
mechanical switch an appropriate debouncing low-pass
filter should be used. If pin MODE is driven by an electronic
circuit or microcontroller then it should remain at the mute
voltage level for at least 100 ms before switching back to
the standby voltage level.
16.3 Output power estimation
The output power in several applications (SE and BTL)
can be estimated using the following expressions:
SE: P_o(1%) = ----R---------^{L------R--+------L----0------.----6-------×}-----V----^P-2---^×--_×---⁽--R-1----_L-^–----t--^m----ⁱ-ⁿ----^×-----f--^o---^s---^c--⁾-----²-
Maximum current:
I_o(peak) = -V----^P----^×-----⁽--R-1----_L^–----₊-t--^m--0--ⁱ-.ⁿ--6--^×-----f--^o---^s--^c----⁾ should not exceed 12 A.
BTL: P_o(1%) = ----R---------^{L------R--+------L----1------.----2-------×}-----2---V----2-^P----_××-----R⁽--1--_L---^–-----t--^m----ⁱ-ⁿ----^×-----f--^o---^s--^c---⁾-----²-
Maximum current:
I_o(peak) = -2---V-----^P----^×-----⁽_R--1---L--^–--₊---t--^m_1---.-ⁱ-2ⁿ----^×-----f--^o---^s--^c---⁾ should not exceed 12 A.
Legend:
R_L = load impedance
f_osc = oscillator frequency
t_min = minimum pulse width (typical 190 ns)
V_P = single-sided supply voltage (so if supply ±30 V
symmetrical, then V_P = 30 V)
P_o(1%) = output power just at clipping
P_o(10%) = output power at THD = 10 %
P_o(10%) = 1.25 × P_o(1%).
16.4 External clock
The minimum required symmetrical supply voltage for
external clock application is ±15 V (equally, the minimum
asymmetrical supply voltage for applications with an
external clock is 30 V).
When using an external clock the duty cycle of the external
clock has to be between 47.5 % and 52.5 %.
A possible solution for an external clock oscillator circuit is
illustrated in Fig.7.
handbook, full pagewidth
VDDA
2 kΩ
0− 0+
11 10
CTC ₁
120 pF
RTC ₂
9.1 kΩ
RCTC _{3 13}
ASTAB−
4
ASTAB+
5
−TRIGGER
6
14 ^VDD
HEF4047BT
7 ^VSS
8
9
+TRIGGER MR
12
RETRIGGER
360 kHz 320 kHz
220
nF
5.6 V
HOP
4.3 V
CLOCK
Fig.7 External oscillator circuit.
GND
MBL468
2003 Jul 28
15